Essential VHDL Errata Errata for Essential VHDL Note: Errata that are numbered in black only apply to books from the first printing. Those numbered in red apply to both the first and second printing. To determine whether you have a book from the first or second printing, open the very first page of the book, that faces the Contents page. There, you should find the printing history. "Second Article, March 1999" indicates that your book came from the second printing.
Chapter 1
In "real" hardware, signals can be thought of as wires. In a more abstract sense, they are analagous to data queues. This is because new values assigned to signals may be queued in time order and "scheduled" at a particular time, from 0ns to the largest time value supported by your VHDL simulator. This abstract model leads to some important properties of signals, which we will discuss later on in the book, most notably in Chapter 8. Every signal has a type. A type is a collection of values that a signal can take. VHDL inherently supports a type known as bit, which allows signals of this (bit) type to take the values '0' or '1'. Additionally, VHDL natively supports the integer type, where signals of this type may take integer values between +(231 - 1) to -(231 -1). However, wires in real hardware take on values other than the '0' or '1'. We might see the high-impedance value, 'Z', or perhaps we might wish to model an unknown value, 'X'. As such, you will most often use the std_logic type,defined in the IEEE 1164 standard, when describing wires as signals. The std_logic type has nine values. These values are as shown in Table 1. Chapter 3
Chapter 4
4.2 The word async on page 63 (4th line of the first paragraph) should read arst. Chapter 5
5.2 The equal1.vhd example (Listing 9) on page 90 uses the std_logic_unsigned package. It should use the numeric_std package, as indicated in the correction. 5.3 On page 76, The second paragraph indicates that numeric_std package defines signed and unsigned as subtypes of std_logic. This is incorrect. Both signed and unsigned types are defined as unconstrained arrays of type std_logic. 5.4 The to_stdlogicvector type conversion function was removed from the final version of the numeric_std package. As such, not all synthesis or simulation tools will support this function. Type conversion in Chapter 5 can be performed without the use of such a function. Paragraphs 3 on page 76 should read as follows: ..... . Hence the need to use countL, followed by a concurrent assignment with the type conversion to equate the count to countL. The type conversion can be performed in this way, since the two types are very similar (signed and unsigned types are arrays of std_logic). Notice also that there is no else condition that...... .This errata changes the following examples: Chapter 5: Listing 1, Listing 2, Listing 3, Listing 4, Listing 5, Listing 6, Listing 7, Listing 8, Listing 10, Listing 11, Listing 13 and Listing 14. Chapter 12: Listing 4, Listing 5, Listing 7. Chapter 13: Listing 2, Listing 3, Listing 8. 5.5 Listing 1 on page 76 should be titled Simple Up-counter, and not Counter Using a Wait Statement. 5.6 Listing 10 on page 91 should be titled Use of to_unsigned Function, and not Use of to_stdlogicvector Function. 5.7 Listing 1 on page 91 should be titled Simple up-counter. Correspondingly, the entry on page xvifor Chapter 5, Listing 1 should also read Simple up-counter. 5.8 The first line of the code example at the bottom of page 87 should read as follows: if (a >= b) then Chapter 6
6.2 Listing 10, pulsefsm.vhd, on page 118 does not indicate the complete listing for the pulse generator design. 6.3 In a state machine, outputs may also condition the next state value (as demonstrated by the PCI state machine developed in this chapter). As such, Figure 1 on page 102 should be modified slightly to reflect this. 6.4 Figure 5 on page 115 has a small ommision. The state waitDelayEnd transitions to loadDelayCnt if condition C1 is asserted. This has been corrected. Chapter 7
7.2 Listing 7 on page 133 is oeconc.vhd and not oecond.vhd. Chapter 9
9.2 The very first library declaration and use clause in Listing 3 on page 177 is unnecessary. While it does not harm, and will certainly compile without any harm to the rest of the design, it is not required and can be eliminated. 9.3 The title of Listing 8 on page 183 should have the keywords for all in italics. 9.4 The comment in Listing 9, at the bottom of page 184 has a spelling error and should read as follows: -- Configuration specifications Chapter 10
10.2 The state machine in Listing 6, on pages 204-207, will not be placed into a known state if it is reset while it is in operation. This is because the current state process, curStProcsimply sets currState(Idle) <= '1'without resetting the other bits in the state vector. This has been corrected. Chapter 11
Chapter 12
ought to work, it does not, since the types do not match. Hence the need to convert Const to an unsigned type.
Just like the operators we saw in Chapter 5, functions can be overloaded. For example, the to_unsigned function may be overloaded as follows:
FUNCTION TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
FUNCTION TO_UNSIGNED (ARG: STD_LOGIC_VECTOR) return UNSIGNED; We can call the function with either a non-negative integer (natural) or a std_logic_vector and the correct one will be picked, depending on the type of the argument passed. Most standard functions, like to_unsigned, accept unconstrained arrays as their inputs. In the case of a std_logic_vector argument, the result returned is of the same dimension and bit-ordering as the argument passed to it. Chapter 13 13.2 Figure 5 on page 270 has a small ommision. The state waitDelayEnd transitions to loadDelayCnt if condition C1 is asserted. This has been corrected. |